Commit 5b17fae0 authored by Stephan Wiederkehr's avatar Stephan Wiederkehr
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added source folder

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#!/bin/sh
nios2-flash-programmer "dtb_v4.2.flash" --base=0x8000000 --epcs --accept-bad-sysid '--cable=USB-Blaster on localhost [USB-0]' --program
#!/bin/sh
export QUARTUS_BINDIR=${QUARTUS_ROOTDIR}/bin
echo "Fetching SW version..."
version=$(grep "sw_version" ../software/dtb_expert/dtb_config.h | tr -dc '[:digit:]' | sed 's/^\(.\{1\}\)/\1./')
if [ -e "dtb_r4s_v${version}.flash" ]
then
echo "Flash file for SW version ${version} already exists - forgot to increment version number?"
echo "Aborting."
else
echo "Generating SOF flash file..."
sof2flash --input="../dtb/output_files/dtb.sof" --output="dtb.flash" --epcs
echo "Generating ELF flash file..."
elf2flash --input="../software/dtb_expert/dtb_expert.elf" --output="dtb_expert.flash" --epcs --after="dtb.flash"
echo "Merging flash files to dtb_r4s_v${version}.flash..."
cat dtb.flash dtb_expert.flash > dtb_r4s_v${version}.flash
rm dtb.flash
rm dtb_expert.flash
echo "Done."
fi
_temp
.qsys_edit
.sopc_builder
db
dtb_system
greybox_tmb
incremental_db
simulation
unused
*.summary
*.smsg
*.rpt
*.pin
*.jdi
*.bak
*~
*.cmp
*.csv
\ No newline at end of file
/* Quartus II 64-Bit Version 13.1.4 Build 182 03/12/2014 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP3C40F484) Path("X:/source/FPGA/pixel-dtb-firmware/dtb/output_files/") File("dtb.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;
PLL_Name clocks:inst14|altpll2:inst5|altpll:altpll_component|altpll2_altpll:auto_generated|pll1
PLLJITTER 49
PLLSPEmax 84
PLLSPEmin -53
PLL_Name clocks:inst14|pll_system:inst23|altpll:altpll_component|pll_system_altpll:auto_generated|pll1
PLLJITTER 37
PLLSPEmax 84
PLLSPEmin -53
PLL_Name dtb_system:inst|dtb_system_ram_ext:ram_ext|dtb_system_ram_ext_controller_phy:dtb_system_ram_ext_controller_phy_inst|dtb_system_ram_ext_phy:dtb_system_ram_ext_phy_inst|dtb_system_ram_ext_phy_alt_mem_phy:dtb_system_ram_ext_phy_alt_mem_phy_inst|dtb_system_ram_ext_phy_alt_mem_phy_clk_reset:clk|dtb_system_ram_ext_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_n5k3:auto_generated|pll1
PLLJITTER 32
PLLSPEmax 84
PLLSPEmin -53
This directory will contain the Quartus II design files for the FPGA.
// === adc_data.v ===========================================================
//
// ADC clock/data timing adjust
// Beat Meier PSI
// 7/21/2017
//
// ==========================================================================
module adc_data
(
input clk,
input serclk,
input res,
input [1:0]cycle,
input davail,
input [4:0]delay,
output reg adc_clk,
input [12:0]data_in,
output reg valid,
output reg [12:0]data_out
);
// (falsepath delay -> *)
// --- coarse adjust: davail -> valid delay
reg [18:0]del;
always @(posedge clk or posedge res)
begin
if (res)
begin
del <= 19'd0;
valid <= 1'b0;
end
else
begin
del <= { del[17:0], davail };
case (delay[4:2])
3'd0: valid <= del[11];
3'd1: valid <= del[12];
3'd2: valid <= del[13];
3'd3: valid <= del[14];
3'd4: valid <= del[15];
3'd5: valid <= del[16];
3'd6: valid <= del[17];
3'd7: valid <= del[18];
endcase
end
end
// --- fine adjust: sampling point
reg ena1;
reg ena2;
always @(posedge serclk or posedge res)
begin
if (res)
begin
ena1 <= 0;
ena2 <= 0;
end
else
begin
ena1 <= (cycle == delay[1:0]);
ena2 <= (cycle == 2'd0);
end
end
// --- data sampling
reg [12:0]s1;
reg [12:0]s2;
always @(posedge serclk or posedge res)
begin
if (res)
begin
s1 <= 13'd0;
s2 <= 13'd0;
end
else
begin
if (ena1) s1 <= data_in;
if (ena2) s2 <= s1;
end
end
// data clock crossing
always @(posedge clk or posedge res)
begin
if (res) data_out <= 13'd0;
else data_out <= s2;
end
// --- ADC clock output
reg [1:0]enac;
always @(posedge serclk or posedge res)
begin
if (res)
begin
enac <= 2'd0;
adc_clk <= 1'b0;
end
else
begin
enac <= {enac[0], ena1};
if (ena1) adc_clk <= 1'b1;
else if (enac[1]) adc_clk <= 1'b0;
end
end
endmodule
# TCL File Generated by Component Editor 12.0sp2
# Wed Jul 10 23:09:04 CEST 2013
# DO NOT MODIFY
#
# adc "adc" v1.0
# Beat Meier PSI 2013.07.10.23:09:04
# ADC gate
#
#
# request TCL package from ACDS 12.0
#
package require -exact qsys 12.0
#
# module adc
#
set_module_property DESCRIPTION "ADC gate"
set_module_property NAME adc
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP DTB
set_module_property AUTHOR "Beat Meier PSI"
set_module_property DISPLAY_NAME adc
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL adc
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file adc.v VERILOG PATH ip/adc/adc.v
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
add_interface_port reset reset reset Input 1
#
# connection point ctrl
#
add_interface ctrl avalon end
set_interface_property ctrl addressUnits WORDS
set_interface_property ctrl associatedClock clock
set_interface_property ctrl associatedReset reset
set_interface_property ctrl bitsPerSymbol 8
set_interface_property ctrl burstOnBurstBoundariesOnly false
set_interface_property ctrl burstcountUnits WORDS
set_interface_property ctrl explicitAddressSpan 0
set_interface_property ctrl holdTime 0
set_interface_property ctrl linewrapBursts false
set_interface_property ctrl maximumPendingReadTransactions 0
set_interface_property ctrl readLatency 0
set_interface_property ctrl readWaitStates 0
set_interface_property ctrl readWaitTime 0
set_interface_property ctrl setupTime 0
set_interface_property ctrl timingUnits Cycles
set_interface_property ctrl writeWaitTime 0
set_interface_property ctrl ENABLED true
add_interface_port ctrl address address Input 2
add_interface_port ctrl write write Input 1
add_interface_port ctrl writedata writedata Input 16
add_interface_port ctrl read read Input 1
add_interface_port ctrl readdata readdata Output 16
set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
#
# connection point adc
#
add_interface adc conduit end
set_interface_property adc associatedClock clock
set_interface_property adc associatedReset reset
set_interface_property adc ENABLED true
add_interface_port adc adc_address export Output 2
add_interface_port adc adc_write export Output 1
add_interface_port adc adc_writedata export Output 16
add_interface_port adc adc_read export Output 1
add_interface_port adc adc_readdata export Input 16
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 64 64 312 272)
(text "adc_readout" (rect 5 0 65 12)(font "Arial" ))
(text "inst" (rect 16 192 33 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "sync" (rect 0 0 24 12)(font "Arial" ))
(text "sync" (rect 21 43 45 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "reset" (rect 0 0 24 12)(font "Arial" ))
(text "reset" (rect 21 59 45 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 96)
(input)
(text "trigger" (rect 0 0 30 12)(font "Arial" ))
(text "trigger" (rect 21 91 51 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 144)
(input)
(text "adc_data[11..0]" (rect 0 0 76 12)(font "Arial" ))
(text "adc_data[11..0]" (rect 21 139 97 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
(pt 0 160)
(input)
(text "adc_or" (rect 0 0 33 12)(font "Arial" ))
(text "adc_or" (rect 21 155 54 167)(font "Arial" ))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 248 40)
(input)
(text "full" (rect 197 120 213 134)(font "Arial" (font_size 8)))
(text "full" (rect 197 32 213 46)(font "Arial" (font_size 8)))
(line (pt 248 40)(pt 232 40))
)
(port
(pt 0 112)
(input)
(text "data_enable" (rect 24 104 93 118)(font "Arial" (font_size 8)))
(text "data_enable" (rect 24 104 93 118)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 248 64)
(output)
(text "writedata[13..0]" (rect -24 0 51 12)(font "Arial" ))
(text "writedata[13..0]" (rect 164 59 239 71)(font "Arial" ))
(line (pt 248 64)(pt 232 64)(line_width 3))
)
(port
(pt 248 88)
(output)
(text "write" (rect -24 0 -2 12)(font "Arial" ))
(text "write" (rect 209 83 231 95)(font "Arial" ))
(line (pt 248 88)(pt 232 88))
)
(drawing
(rectangle (rect 16 16 232 192))
)
)
// adc_readout.v
`timescale 1 ns / 1 ps
module adc_delay
(
input clk,
input reset,
input sync,
input [5:0]del,
input in,
output out
);
reg running;
reg [5:0]cnt;
wire start = in && !running;
wire stop = cnt == 0;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
running <= 0;
cnt <= 0;
end
else if (sync)
begin
if (start) running <= 1;
else if (stop) running <= 0;
if (start) cnt <= del;
else if (!stop) cnt <= cnt - 1;
end
end
assign out = running && stop;
endmodule
module adc_timeout
(
input clk,
input reset,
input sync,
input [15:0]len,
output [15:0]size,
input start,
input stop,
output reg running
);
reg [15:0]cnt;
wire timeout = cnt == len;
always @(posedge clk or posedge reset)
begin
if (reset) running <= 0;
else if (sync)
begin
if (stop || timeout) running <= 0;
else if (start) running <= 1;
end
end
always @(posedge clk or posedge reset)
begin
if (reset) cnt <= 0;
else if (sync)
begin
if (running) cnt <= cnt + 1;
else if (start) cnt <= 0;
end
end
assign size = cnt;
endmodule
module adc_readout
(
input clk,
input sync,
input reset,
input [1:0]avs_ctrl_address,
input avs_ctrl_write,
input [15:0]avs_ctrl_writedata,
input avs_ctrl_read,
output [15:0]avs_ctrl_readdata,
input run,
input trig1,
input trig2,
input tin,
input tout,
// ADC port
input [11:0]adc_data,
input adc_or,
// FIFO port
output write,
output [15:0]writedata,
output [5:0]TP
);
wire start;
wire stop;
wire running;
// control registers
reg single;
reg cont;
reg [1:0]ssel;
reg psel;
reg [5:0]sdel;
reg [5:0]pdel;
reg [15:0]len;
wire [15:0]size;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
single <= 0;
cont <= 0;
ssel <= 0;
psel <= 0;
sdel <= 0;
pdel <= 0;
len <= 0;
end
else if (avs_ctrl_write)
begin
if (avs_ctrl_address == 0)
begin
cont <= avs_ctrl_writedata[0];
if (!(start || running)) single <= avs_ctrl_writedata[1];
end
if (avs_ctrl_address == 1) { ssel, sdel } <=
{ avs_ctrl_writedata[15:14], avs_ctrl_writedata[5:0] };
if (avs_ctrl_address == 2) { psel, pdel } <=
{ avs_ctrl_writedata[15:14], avs_ctrl_writedata[5:0] };
if (avs_ctrl_address == 3) len <= avs_ctrl_writedata;
end
else if (start) single <= 0;
end
assign avs_ctrl_readdata = (avs_ctrl_address == 3) ?
size : {13'h0000, running, single, cont};
// start select
reg s;
always @(*)
begin
case (ssel)
0: s <= 0;
1: s <= trig1;
2: s <= trig2;
3: s <= tin;
endcase
end
wire s_gated = s && run && (cont || single);
adc_delay sdelay(clk, reset, sync, sdel, s_gated, start);
// stop select
wire p_gated = tout && psel;
adc_delay pdelay(clk, reset, sync, pdel, p_gated, stop);
// burst generator
reg start_reg;
// reg stop_reg;
wire [12:0]adc_reg = { adc_or, adc_data };
always @(posedge clk or posedge reset)
begin