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version 1.0.0-rc.24

leonarski_f requested to merge 2410-new-fpga-release into main

New FPGA functionality:

  • EIGER supports 8, 16 and 32-bit data input (for 8-bit mode at half performance; for 32-bit "real" depth is 23-bit + 1-bit signed)
  • Output possible to 8, 16 and 32-bit data
  • Threshold is applied before summation
  • Pixel mask can be applied on FPGA
  • Mark pixels with ADC content = 0 as bad pixels
  • FPGA stores semantic version information (access via /sys/class/misc/jfjoch.../version)

New software functionality:

  • Long summation (above 256 frames) done on CPU
  • Mechanism to save arbitrary data to HDF5 file
  • ZeroMQ preview has option to send start message
  • Rework pixel mask + add statistics displayed in web interface

Bug fixes:

  • Web-based image preview not displayed in web view
  • Error handling if CUDA driver is not installed
  • Handle properly when upload file is not a proper TIFF
  • jfjoch_action_test not working with HLS simulation

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