Improvement in internal frame generator
- Jan 18, 2024
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leonarski_f authored2c54b17b
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leonarski_f authored9a6d33e4
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leonarski_f authored29b6a188
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leonarski_f authored9fa9a054
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leonarski_f authored71a491c5
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leonarski_f authored987652e4
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leonarski_f authored03dc0567
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leonarski_f authored056c7ab3
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leonarski_f authored
FPGA: add idle signal to UDP and sls_detector cores (for simulation purposes, might later connect them to action_config.v)
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leonarski_f authoreda065e2a2
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leonarski_f authored497b7ec8
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leonarski_f authorede83f40cd
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leonarski_f authored1b690efa
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leonarski_f authoredcc7abc9c
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leonarski_f authored
HLSSimulatedDevice: All network cores are parallel, but: (1) ARP and ICMP are removed, (2) cores are called if there are actually some data available
27603077 -
leonarski_f authoredcadc1fbc
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leonarski_f authored7fea117e
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leonarski_f authored8b025f51
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